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ICs for Consumer Electronics MEGATEXT and MEGATEXT PLUS ICs
SDA 5273 / SDA 5275 SDA 5273-2 / SDA 5275-2
Data Sheet 1997-09-01
MEGATEXT(R) and MEGATEXT PLUS ICs SDA 5273 / SDA 5275 SDA 5273-2 / SDA 5275-2 Revision History: 1997-09-01 Previous Releases: Page 20 11.96 Subjects (changes since last revision) Now also covers SDA 5275-2 and SDA 5273-2 versions; Reset/chip initialization update
Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage. Operating Range In the operating range the functions given in the circuit description are fulfilled. For detailed technical information about "Processing Guidelines" and "Quality Assurance" for ICs, see our "Short Form Catalog".
Edition 1997-09-01 Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1997. All Rights Reserved. As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.
SDA 5273 / 75 SDA 5273-2 / 75-2
Contents
Page
1 1.1 1.2 2 3 4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MEGATEXT(R) is a registered trademark of Siemens AG
Semiconductor Group
3
1997-09-01
MEGATEXT(R) and MEGATEXT PLUS ICs
SDA 5273 / 75 SDA 5273-2 / 75-2
CMOS IC
Preliminary Data 1
q q q q q q
Features
Single chip teletext IC Analog CVBS-input with onchip clamping circuitry Slicer Supports level 1, 2.5 and 3.5 ETSI teletext standard Stores up to 14 teletext pages on chip Stores up to 2048 teletext pages with external 16 M memory q SDA 5275: full level 2.5 processing Analog RGB-output 41 latin script languages 12 x 10 character size Parallel display attributes 64 from 4096 colors selectable Enhanced flash modes Dynamically redefinable character set (DRCS, PCS) Pixel graphics Fullscreen display (64 x 32 or 80 x 24 character positions) Horizontal and vertical scrolling Graphic cursors 4:3 and 16:9 display Multinorm display (50/60/100/120 Hz) RISC-processor Firmware downloadable I2C / 3 wire UART-interface (1 Mbit/s) Independent clocks for acquisition and display Tools for greatly simplified software development
P-LCC-68-1
q q q q q q q q q q q q q q q q q q
P-SDIP-52-1
q 24-Kbyte on-chip reconfigurable DRAM q 44160-bit character ROM q One external crystal for all standards
Type SDA 5273 / 75 P SDA 5273 / 75 S SDA 5273-2 / 75-2P SDA 5273-2 / 75-2S SDA 5273C / 73-2C P SDA 5273C / 73-2C S
Ordering Code on request on request on request on request on request on request
Package P-LCC-68-1 P-SDIP-52-1 P-LCC-68-1 P-SDIP-52-1 P-LCC-68-1 P-SDIP-52-1
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Pin Configuration (top view) P-SDIP-52-1
CLK- O TCSQ/FLD VS/VCS HS X OUT XIN GPO TM CVBS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
UEP04657
NTQ CEN SDA SCL CORQ BLAN B G R
2
V DD 1 V DD A V SSA 1 V DD 2
RES
V SS 1
RGB-GND
V SSA 2 V SS2 V BB /N.C. V SS3
CASQ
V DD 3 V REF V DD 4
A8 A7 A6 A5 A4 A3 A2 A1 A0
V SS4
D3 D2 D0 D1 WEQ RASQ A11 A10 A9
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1.1
Pin Definitions and Functions Symbol CLK-IO TCSQ/FLD VS/VCS HS XOUT XIN GPO TM CVBS Function System clock input/output Composite sync output/ field output Vertical sync input/output Horizontal sync input/output 20.5-MHz crystal oscillator output 20.5-MHz crystal oscillator input General purpose output Testpin, leave open or connect to VSS CVBS-video signal input + 5 V digital supply + 5 V analog supply Analog ground + 5 V digital supply Chip reset + 5 V digital supply + 3 V reference voltage input + 5 V digital supply External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address Row address strobe (DRAM) Write enable (DRAM) External DRAM-data
Pin No. P-SDIP-52-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD1 VDDA VSSA1 VDD2
RES
VDD3 VREF VDD4
A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A10 A11 RASQ WEQ D1
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1.1
Pin Definitions and Functions (cont'd) Symbol D0 D2 D3 Function External DRAM-data External DRAM-data External DRAM-data 0 V digital supply Column address strobe 0 V digital supply Substrate bias voltage N.C.1) 0 V digital supply Analog ground RGB-ground 0 V digital supply Analog red display output Analog green display output Analog blue display output Blanking signal open drain output Contrast reduction open drain output Bidirectional I2C Bus clock port Bidirectional I2C Bus data port
Pin No. P-SDIP-52-1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
1)
VSS4
CASQ
VSS3 VBB VSS2 VSSA2
RGB-GND
VSS1
R G B BLAN CORQ SCL SDA I2CEN INTQ
I2C Bus enable
Interrupt request output to ext. controller
Depends on version. Please refer to the respective Delta Specification.
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Pin Configuration (top view)
P-LCC-68-1
TM GPO XIN XOUT HS VS/VCS TCSQ/FLD CLK-IO INTQ 2 CEN SDA SCL CORQ BLAN B G R
9 CVBS V DD1 V DDA V SSA1 N.C. N.C. VDD2 RES N.C. N.C. N.C. VDD3 N.C. VREF N.C. VDD4 A8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
V SS1
RGB-GND V SSA2 N.C. V BB /N.C. V SS2 N.C. N.C. N.C. N.C. N.C. V SS3 N.C. N.C. N.C. CASQ V SS4
A7 A6 A5 A4 A3 A2 A1 A0 A9 A10 A11 RASQ WEQ D1 D0 D2 D3
UEP05514
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1.2
Pin Definitions and Functions Symbol INTQ CLK-IO TCSQ/FLD VS/VCS HS XOUT XIN GPO TM CVBS Function Interrupt request output to ext. controller System clock input/output Composite sync output/ field output Vertical sync input/output Horizontal sync input/output 20.5-MHz crystal oscillator output 20.5-MHz crystal oscillator input General purpose output Testpin, leave open or connect VSS CVBS-video signal input + 5 V digital supply + 5 V analog supply Analog ground Not connected Not connected + 5 V digital supply Chip reset Not connected Not connected Not connected + 5 V digital supply Not connected + 3 V reference voltage input Not connected + 5 V digital supply External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address
Pin No. P-LCC-68-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD1 VDDA VSSA1
N.C. N.C.
VDD2
RES N.C. N.C. N.C.
VDD3
N.C.
VREF
N.C.
VDD4
A8 A7 A6 A5 A4 A3 A2
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1.2
Pin Definitions and Functions (cont'd) Symbol A1 A0 A9 A10 A11 RASQ WEQ D1 D0 D2 D3 Function External DRAM-address External DRAM-address External DRAM-address External DRAM-address External DRAM-address Row address strobe (DRAM) Write enable (DRAM) External DRAM-data External DRAM-data External DRAM-data External DRAM-data 0 V digital supply Column address strobe Not connected Not connected Not connected 0 V digital supply Not connected Not connected Not connected Not connected Not connected 0 V digital supply Substrate bias voltage N.C.1) Not connected Analog ground RGB-ground 0 V digital supply Analog red display output Analog green display output Analog blue display output
Pin No. P-LCC-68-1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
1)
VSS4
CASQ N.C. N.C. N.C.
VSS3
N.C. N.C. N.C. N.C. N.C.
VSS2 VBB
N.C.
VSSA2
RGB-GND
VSS1
R G B
Depends on version. Please refer to the respective Delta Specification.
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1.2
Pin Definitions and Functions (cont'd) Symbol BLAN CORQ SCL SDA I2CEN Function Blanking signal open drain output Contrast reduction open drain output Bidirectional I2C Bus clock port Bidirectional I2C Bus data port
Pin No. P-LCC-68-1 64 65 66 67 68
I2C Bus enable
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2
Electrical Characteristics
Absolute Maximum Ratings Parameter Supply voltage Ambient temperature Storage temperature Power consumption Electrostatic discharge Symbol Limit Values min. typ. max. 6.0 70 125 1.8 2000 V C C W V 100 pF, 1 k HBM according to MIL-standard 883 method 3015.7 0 0 - 20 Unit Test Condition
VDD TA Tstg Ptot
Characteristics TA = 0 to 70 C Parameter Symbol Limit Values min. Supply Voltages typ. max. Unit Test Condition
VDDD VDDA
Supply Currents
4.7 4.7
5.0 5.0
5.3 5.3
V V
VDDD = VDDA!
IDDD IDDA
Inputs Tristate of Outputs: I2CEN, HS, VS, GPO, RES, D0-D3 H-input voltage L-input voltage Input capacitance Input leakage current Input current RES
200 60
mA mA
20 pF load per pin
VIH VIL CI IL IIH
2.0 - 1.0
VDDD
0.8 7 10 100
V V pF A A
VIH = 5.5 V VIH = 5.5 V
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Characteristics (cont`d) TA = 0 to 70 C Parameter Symbol Limit Values min. typ. max. Unit Test Condition
Outputs TTL-Outputs: A0-A11, D0-D3, RASQ, CASQ, WEQ, HS, VS, GPO, INTQ, TCSQ H-output voltage L-output voltage Load capacitance Transition period
VOH VOL CL tr, tf
2.4 0
VDDD
0.4 50 15
V V pF ns
- IOH = 0.2 mA
IOL = 1.6 mA
Open Drain Outputs: BLAN, CORQ Sink current L-output voltage H-output voltage BLAN = 1: BLAN = 0; CORQ = 1; CORQ = 0;
IOL VOL VOH
5 0.4
mA V V
low level output
IOL = 2 mA
VDDD
display MEGATEXT RGB-outputs display other source switch contrast reduction OFF switch contrast reduction ON
Sourcefollower Output: CVBS at pin TCSQ DC-offset to CVBS-input Gain Output current Output impedance Edge response 1.2 V
G IO RO tr
0.9
0.9 mA 200 1 s CVBS = 1 V, TCSQ = 0 V CVBS = 1 V 10 to 90 %, 1 Vpp, CL = 50 pF
Sync Timing: HS, VS, TCSQ Sync Output Waveforms Pulse width HS Pulse width VS VCS-waveform TCSQ-waveform
tWH tWH
2 1
s line see diagram 6a, b see diagram 6a, b
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Characteristics (cont'd) TA = 0 to 70 C Parameter Symbol Limit Values min. Output Timing: HS, VS, TCSQ Hold and delay time with respect to 24-MHz system clock output: Delay time Hold time Delay time Hold time Input Timing: HS, VS No synchronous input mode specified! Clock Input/Output (see diagram 1) Clock Input H-input voltage L-input voltage Input capacitance Input leakage current Period Transition time Symmetry ratio Clock Output H-output voltage L-output voltage Load capacitance Period Transition time Symmetry ratio typ. max. Unit Test Condition
tOD tOH
0
20
ns ns
see diagram 2 see diagram 2 not specified not specified
Hold and delay time with respect to 24-MHz external system clock input:
VIH VIL CI Il
Tc Tc
2.0 - 1.0
VDDD
0.8 7 10
V V pF A
VIH = 5.5 V
24-MHz clock 27-MHz clock
40 35 3 0.43 0.57 ns
tCR, tCL tCH/tC
VOH VOL CL
TC
2.4 0 41.7
VDDD
0.4 50 5
V V pF ns ns ns
- IOH = 0.2 mA
IOL = 1.6 mA
20.5-MHz crystal
tCR, tCF tCH/tC
0.3
0.5
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Characteristics (cont'd) TA = 0 to 70 C Parameter Symbol Limit Values min. RGB-Outputs typ. max. Unit Test Condition
VREF = 3 V no resistive load RGB-GND = 0 V
Pin capacitance Output voltage range RGB-amplitude DC-offset voltage Clamp level DAC-resolution Diff. non-linearity Int. non-linearity Output tracking Output resistance 3-dB bandwidth - 0.5 - 0.5 - 0.5
CP
0 1.1 0.7 1.25 0.8 0 4
7 2.2 1.55 1.0
V V V V V bit R83: RGB-GAIN (4:0) = 1FH R83: RGB-LEVL (2:0) = 7
0.5 0.5 0.5 270 10
LSB LSB LSB MHz
R83: RGB-GAIN (4:0) = 1FH RGB-LEVL (2:0) = 0
RO
1 ---------------------2 R O C L
CL = 50 pF
Bus Connection: SDA, SCL, I2CEN (see diagram 4) Inputs: SDA, SCL H-input voltage L-input voltage Input capacitance Input leakage current
VIH VIL CI IL
3.0 - 1.0
VDDD
1.5 7 10
V V pF A
VIH = 5.5 V VDD = 0 V ... 5.5 V
For modes with external clock MEGATEXT may only be operated in freerun mode as sync master. HS may not be used as an input in these cases. The RGB-output voltage is proportional to VREF.
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Characteristics (cont'd) TA = 0 to 70 C Parameter Symbol Limit Values min. Open Drain Outputs: SDA, SCL L-output voltage Sink current typ. max. Unit Test Condition
VOL IOL
0
0.4 10
V mA
IOL = 3 mA
I2C-Mode Timing
MEGATEXT is an I2C-slave transmitter/receiver. The Siemens I2C Bus specification applies. SCL-frequency Transition time Bus capacitance Bus free before start Hold time start L-time clock H-time clock Set-up time start Hold time SDA Set-up time SDA Set-up time SDA at stop Output fall time M3L-Mode Timing The MEGATEXT M3L-Bus is specified in accordance with the standard USART-interface of micro controller SDA 30C162. SCL-frequency L-time clock H-time clock SCL-load capacitance Set-up time SDA-input to SCL-falling edge Hold time SDA-input from SCL-falling edge
fSCL tr, tf CBUS tBUF tHSTA tLOW tHIGH tSUSTA tHDDAT tSUDAT tSUSTO tFO
0
100 2 400
kHz s pF s s s s s s ns s
I2CEN = high
4.7 4.0 4.0 4.0 4.0 0 250 4.0 0.2
s
3 V to 1 V
fSCL tL tH CSCL tDSL tDHH
0 400 400
1.0
MHz ns ns
20.48-MHz crystal
200 100 400
pF ns ns
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Characteristics (cont'd) TA = 0 to 70 C Parameter Symbol Limit Values min. M3L-Mode Timing (cont'd) Set-up time SDA to I2CENrising edge Set up time I2CEN to SDAfalling edge typ. max. Unit Test Condition
tIM tIS tIH tDO
400 400 1000 400 600
ns ns ns ns
I2CEN-high time
Delay from SCL-falling edge until SDA-open drain output stage changes impedance L-SDA level output impedance
100
The resulting delay of SDA-output data is the sum of the open drain stage plus the time determined by the bus capacitance and the external pullup resistor or the impedance of the internal open drain pulldown transistor respectively. Wait condition
I2CEN = 0
To force the M3L-master to interrupt the transmission sequence until MEGATEXT is ready for more data, MEGATEXT can force down SCL after the transmission of a complete byte. At that time the bus master has to switch its SCL-output to high impedance and check the state of SCL afterwards.During SCL check I2CEN has to be low. Delay from SCL-rising edge to SCL forced low for WAITcondition SCL-pullup time at the end of WAIT Reference Voltage: VREF Voltage level Input leakage current
tDWAIT
500
750
ns
An internal pullup transistor restores SCL high level at the end of the WAIT-condition.
tRWAIT
70
100
ns
VREF Il
2.8 - 10
3.0
3.5 10
V A
VREF = 3 V
VREF influences the DAC-range, the CVBS-output at pin TCSQ and the CVBS-ADC range.
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Characteristics (cont'd) TA = 0 to 70 C Parameter Symbol Limit Values min. CVBS-Input and ADC (VREF = 3 V) Input leakage current Input capacitance Ext. coupling capacitance Sensitivity of clamp level to current leakage/injection ADC-range CVBS-sync amplitude Crystal Oscillator: XIN, XOUT Bias resistance between XIN, XOUT Small signal voltage gain Feedback capacitance Pin capacitance Crystal Nominal frequency Effect of temperature and accuracy of adjustment Temperature range Resonant impedance Equivalent parallel C Crystal load Ext. capacitors typ. max. Unit Test Condition
Il CP CCPL
- 1.0 100 - 15 1.7 0.1
1.0 45 15 2.0
A pF nF mV/ A V V
CVBS = 2 V
Il = 2 A CCPL = 100 nF VREF = 3 V
RXbias GV CFB CP
60 8
120 13
180
k 100 kHz, 50 mVpp
4.0 7.0
pF pF
fO
df/fO -5% 0
20.48 +5% 70 40 15 0.1 15
MHz
TA ZR CL C1,2
C pF mW pF
The center frequency of the MEGATEXT horizontal PLL is proportional to the crystal frequency. In PAL-mode the centre frequency is 15.625 kHz for the typical crystal frequency of 20.48 MHz. Deviations from the typical crystal frequency will shift the range of the horizontal frequencies where the PLL is able to lock.
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Characteristics (cont'd) TA = 0 to 70 C Parameter Symbol Limit Values min. DRAM-Interface (see diagram 5) The external DRAM is operated in page mode. The timing of the DRAM-interface signals are specified below. Cycle time Address hold time from RAS Address hold time from CAS Address set-up time from RAS Address set-up time from CAS L-time RAS L-time CAS H-time RAS H-time CAS Refresh period Write Cycle L-time WE Data set-up time to CAS WE set-up time to CAS Data hold time from CAS Data hold time from WE Read Cycle H-time WE (output enable) Access time from CAS Data hold time of DRAM typ. max. Unit Test Condition
tWC tRAH tCAH tASR tASC tRASP tCASL tRP tCP
420 25 60 5 5 280 70 140 70 20
500
550
ns ns ns ns ns ns ns ns ns ms
tWEL tDS tRCS tDH tOHZ
210 100 0 55 10
ns ns ns ns ns
tOEL tCAC tOFF
210 60 40
ns ns ns
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Characteristics (cont'd) TA = 0 to 70 C Parameter Symbol Limit Values min. Reset/Chip Initialization A power-on reset or a reset pulse at pin RES lead to a hardware reset and a software initialization of registers and internal DRAM. During initialization bus transfers are not allowed. At / after power-on a reset pulse at pin RES is necessary. RES may return to 0 after the supply voltage reached its lower limit for chip function (4.7 V). This may be achieved by a capacitor C between RES and VDD and by a resistor R between RES and VSS. The dimensions of R and C depend on the worst case rise time of VDD. Initialization time after power- tINIT on or falling edge of RES Pulse width RES High level at pin RES causes chip reset. In rare cases, the IC may remain in a permanent reset state after power up, depending on the applicational context. After power up, the software should check proper operation. In case the Megatext does not react properly, power supply should be switched off for at least 3 s. After that, power supply can be switched on again. Other Items Horizontal frequency pull-in range of CVBS-PLL: 15 15.2 Horizontal frequency pull-in range of display-PLL: 15 15.625 16.2 15.748 16.3 15.625 16.2 kHz kHz kHz 20.48 MHz crystal PAL 20.48 MHz crystal NTSC 20.48 MHz crystal 100 25 ms typ. max. Unit Test Condition
VDD greater 4.7 V
If the supply voltage drops below VDD min, the IC has to be reset by pin RES. ns
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3
Diagrams
t CR
t CF
2.0 V
CLK 1.5 V 0.8 V
t CH tC
t CL
UET04660
Timing Diagram 1
2.4 V CLK_OUT 1.5 V 0.8 V
t OD t OH t OH
2.4 V HS VS 0.8 V
tW t OD
UET04662
Timing Diagram 2
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2 CEN
V IH V IL t HIGH t f t LOW V IH V IL t BUF t SUSTA t SUDAT t HDDAT t SUSTO V IH V IL
UET04815
SCL
t BUF
SDA
Timing Diagram 3a I2C-Bus Mode
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2 CEN
V IH V IL t BUF t IS t HIGH t f t LOW t r t IM V IH V IL t DS t DHH t DSL t DO t DHH V IH V IL V OL t DWAIT t RWAIT V IH V IL V OL
UET04816
t BUF
SCL
SDA
Wait Condition
SCL
WAIT
Timing Diagram 3b M3L-Bus Mode
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t WC
A0... A11 WEQ Row Address Column Address Column Address
t WE
t WEL
D0... D3 Data from SDA 527x
t OHZ
Data from SDA 527x
t RP t RAH
RASQ
t DS t DH
t DS t DH
t RASP t ASR t CP
CASQ
t CAH t CP
t ASC
t CASL
t CASL
UET04663
Timing Diagram 4a DRAM-Page Mode Write Cycle
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t RC
A0... A11 Row Address Column Address Column Address
t OE
WEQ
t OEL
D0... D3 Data from RAM Data from RAM
t RP t RAH
RASQ
t CAC
t OFF t CAC
t OFF
t RASP t ASB t CP
CASQ
t CAH t CP
t ASC
t CASL
t CASL
UET04664
Timing Diagram 4b DRAM-Page Mode Read Cycle
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a) Line Sync Pulse
b) Equalizing Pulse
0
4.7
64
t [ s] t [ s]
0 2.35 c) Main Pulse 0
32 34.35
64
27.3 32 Timing with Tolerances 100 ns
59.3 64
t [ s]
VCS 622 (309) VCS 310 TCS 622 (309) TCS 310 TCS 309 (310) (621) (623) 310 (311) (622) (624) 311 (312) (623) (625) 312 (313) (624) (626) 1 (1) 2 (2) 3 (3) 4 (4) 5 (5) 6 (6) 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) NonInterlaced -312/312 Lines -313/312 Lines -626/624 Lines
UED04865
623 (310)
624 (311)
625 (312)
1
2
3
4
5
6
311
312
313
314
315
316
317
318
319 Interlaced
623 (310)
624 (311)
625 (312)
1
2
3
4
5
6 Interlaced
Timing Diagram 5a VCS and TCS in PAL Freerun Mode
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a) Line Sync Pulse
0 4.7 63.6
t [s]
b) Equalizing Pulse
0 2.3 31.8 34.1 63.6
t [s]
c) Main Pulse
0 27.1 31.8 58.9 63.6
t [s]
VCS
522 (259) 523 (260) 524 (261) 525 (262) 1 2 3 4 5 6
VCS
260 261 262 263 264 (1) 265 (2) 266 (3) 267 (4) 268 (5) 269 (6)
TCS
522 (259) 523 (260) 524 (261) 525 (262) 1 2 3 4 5 6
Interlaced
TCS
260 261 262 263 264 (1) 265 (2) 266 (3) 267 (4) 268 (5) 269 (6)
Interlaced
TCS
259 (260) (521) (523) 260 (261) (522) (524) 261 (262) (523) (525) 262 (263) (524) (526) 1 (1) 2 (2) 3 (3) 4 (4) 5 (5) 6 (6)
NonInterlaced -262/262 Lines -263/262 Lines -526/524 Lines
UED04872
Timing Diagram 5b VCS and TCS in NTSC Freerun Mode
Semiconductor Group
27
1997-09-01
SDA 5273 / 75 SDA 5273-2 / 75-2
TTL HS VS TTL TCSQ
1.15 Vpp 270 TTL INTQ 2 CEN SDA SCL G B R
V DD
4.7 k
22 pF
22 pF 20.48 MHz
4.7 k
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
Contrast 150 Reduction
CVBS 2 Vpp
100 nF
150 Blank
TM GPO XIN XOUT HS VS TCSQ CLK INTQ 2 CEN SDA SCL CORQ BLAN B G R
V DD
10
F
10 k
V DD
5V
V DD V DD
470
Ref. ZD 3V 220 nF
V SS
220 nF
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A7 A6 A5 A4 A3 A2 A1 A0 A9 A10 A11 RASQ WEQ D1 D0 D2 D3
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
CVBS V DD1 V DDA V SSA1 N.C. N.C. V DD2
V SS1
RGB-GND V SSA2 N.C. V BB
RESET N.C. N.C. N.C. V DD3 N.C. V REF N.C. V DD4 A8
SDA 527x
V SS2 N.C. N.C. N.C. N.C. N.C. V SS3
N.C. N.C. N.C. CASQ V SS4
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
220 nF
100 k
DRAM
UES04659
Application Circuit
Semiconductor Group
28
1997-09-01
SDA 5273 / 75 SDA 5273-2 / 75-2
4
Package Outlines
P-LCC-68-1 (SMD) (Plastic Leaded Chip Carrier)
5.08 max 0.5 min 3.5 0.2
1.2 x 45
1.27 0.43 0.1
0.81 max 0.18 M A-B D 68x 20.32 D 0.1
0.2
23.3 0.3 24.21 0.07 1) 25.28 -0.26
0.38 M A-B D 34x
A
B
0.5 x 45 3x
68 1
1.1 x 45
Index Marking
24.21 0.07 1) 25.28 -0.26
1) Does not include plastic or metal protrusions of 0.15 max per side
GPL05099
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 29
Dimensions in mm 1997-09-01
SDA 5273 / 75 SDA 5273-2 / 75-2
Plastic Package, P-SDIP-52-1 (Plastic Dual In-Line Package)
0.5 min 4.83 max
15.24 +0.7
3.43 -0.4
1.78
1.3 max
0.46 0.1
0.25 M 52x
0.25 0.05 14.02 0.25 15.24 +1.7
52
27
1
Index Marking
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 30
Dimensions in mm 1997-09-01
GPD05262
46.1 -0.3
26
0.25 max

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